AI ASIC Design Engineer

We’re seeking an AI semiconductor design engineer to help design and develop next-generation AI computing hardware. In this role, you will work on the architecture, microarchitecture, RTL design, and optimization of AI accelerators and related SoC components that power high-performance machine learning workloads. This position is important because efficient AI hardware is becoming a core foundation for scalable, low-power, and high-throughput AI systems.

What you will do

• Design and implement AI accelerator architectures, compute blocks, memory subsystems, interconnects, and SoC components for machine learning workloads.
• Develop RTL using Verilog/SystemVerilog and collaborate closely with verification, physical design, software, and architecture teams.
• Analyze and optimize performance, power, area, and timing trade-offs across the design lifecycle.
• Translate AI model requirements and workload characteristics into efficient hardware features and design specifications.
• Participate in design reviews, debugging, simulation, synthesis, and pre-silicon validation activities.
• Work with EDA tools and design methodologies to support robust and scalable chip development.

What we look for

• Strong background in digital logic design, computer architecture, semiconductor design, or related engineering fields.
• Hands-on experience with RTL design using Verilog or SystemVerilog.
• Understanding of AI/ML workloads, neural network operations, or AI accelerator architectures.
• Experience with SoC design concepts such as memory hierarchy, bus protocols, DMA, cache, NoC, or high-speed interfaces.
• Ability to analyze hardware performance and make informed design trade-offs.
• Strong problem-solving skills and ability to work effectively in a cross-functional engineering environment.
• Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Nice to have

• Experience designing AI accelerators, GPUs, NPUs, TPUs, DSPs, or custom ASICs.
• Familiarity with model-to-hardware mapping, quantization, sparsity, tensor operations, or compiler-hardware co-design.
• Experience with synthesis, static timing analysis, formal verification, UVM-based verification, or FPGA prototyping.
• Knowledge of advanced memory systems such as HBM, GDDR, SRAM architecture, or memory bandwidth optimization.
• Experience with performance modeling using C/C++, Python, SystemC, or similar tools.
• Tape-out experience or participation in full chip development from architecture to silicon validation.